MrKWatkins/ZXSpectrumNextTests — test inventory

The main community acceptance suite for Spectrum Next emulators and FPGA cores: .nex/.tap programs with reference screenshots from real hardware. Statuses flip from planned to live results as each test is wired into the headless harness (ZX Play work item #137). Upstream: https://github.com/MrKWatkins/ZXSpectrumNextTests.

base — CPU and register fundamentals

TestStatusNotes
Z80N pass All 23 Z80N instructions OK with green border (matches the real-hardware photo). First run caught LDDX/LDDRX direction and LDWS flags — fixed in pkg/z80
Z80Nc2 pass Core-2 additions (barrel shifts, JP (C)) all OK; caught the JP (C) I/O-jump semantics bug — fixed in pkg/z80
NextReg_defaults pass Full 256-cell verdict grid asserted (attribute decode). Matches the core-3.1.5 board photo except: 7 cells the board shows yellow from NextZXOS boot side-effects (OS-less harness earns strict green) and NR$0A/NR$10 red on core 3.2.x semantics (we follow master zxnext.vhd + MAME 0.282; test targets 3.1.5). Audit fixed: copper NR$61-$63 byte-granular cursor, NR$8E paging-lock bypass, NR$7F/$82-$89 reset defaults, ULA-first classic palette default
Copper pass Full visible surface asserted: both self-reported counters 03F3 (board + MAME), all five Swedish flags incl. the over-left-border one, the horizontal-wait >= probe's single yellow pixel, the Z80-animated line with its left-border segment one row lower, rulers and background. Drove the cycle-paced copper (MOVE 2 / NOOP 1 cycles at 28MHz, mode-transition-only list restart) and the live-palette ULA/border render (ULANext decode). Residual precision: palette sampled once per 7MHz pixel, so half-pixel flag detail collapses to one colour per pixel
DMA pass Full verdict surface asserted: all 24 A->B/B->A mode cells (IO rows yellow), short-init 4+4+1 and CONTINUE 4+4 areas, the 16-byte read-back stream (adjudicated against dma.vhd — the board photo predates the hex display and MAME 0.281's read-back is non-conformant), the auto-restart prescaler burst fill and the IM2 CPU-speed stepping. Fixed: $BF read-status, read-state machine, $83 disable, burst auto-restart, monotonic burst clock, turbo-scaled prescaler delay, harness DMA IO-bus wiring

Graphics — Layer 2 and layer mixing

TestStatusNotes
Layer2Colours planned
Layer2Port planned Port $123B paging behaviour
Layer2Scroll planned
LayersMixingHiCol planned Timex hi-colour mixing
LayersMixingHiRes planned Timex hi-res mixing
LayersMixingLoRes planned LoRes mixing
LightenDarken_L2_ULA planned Additive blend modes — exercises a catalogued known gap (blend modes 6/7 approximated)
NextReg0x69 planned Display control register

Sprites

TestStatusNotes
Transparency planned
Relative planned Anchor/relative sprite groups
BigSprite planned
BigSprite4b planned 4bpp variant
ScanlineDelay planned Exercises the catalogued known gap: per-line sprite bandwidth limit not modelled

ULA — palettes, transparency, scroll

TestStatusNotes
DefaultTransparency planned
BorderTransparencyFallback planned NR$4A fallback colour
ChangePaletteTransparency planned
ChangePaletteTransparency_v2 planned
ChangePaletteTransparency_v3 planned
ClassicPaletized planned Next ULA palette on the classic screen — relates to the catalogued ULA-palette gap
UlaScroll planned

Interrupts

TestStatusNotes
HaltAfterDisable pass DI + HALT must hang forever; asserted via the border-colour signature

Timing

TestStatusNotes
Changing8kBank planned MMU bank-switch timing
Changing8kBank_NoContention planned
ScanlineReadingAndInterrupt planned NR$1E/$1F raster reads vs the frame interrupt

Misc — DMA deep dives

TestStatusNotes
ZilogDMA planned Zilog-DMA-mode behaviour
DmaInteractive manual Interactive; includes real Zilog hardware photos — manual comparison rather than CI

ZX48 / ZX128 classic tests

TestStatusNotes
Z80BlockInstructionFlags pass Interrupted-block flags (David Banks) — matches real hardware (blockRepeatFlags); hard regression guard
Z80CcfScfOutcomeStability pass SCF/CCF outcomes must be deterministic frame over frame
Z80IntSkip (basics) pass NOP benchmark, DI inhibition, SCF/CCF chains, IFF2 reads during int-ack
Z80IntSkip (prefix/EI inhibition) pass Prefix/EI interrupt inhibition + level-triggered /INT pulse re-entry — conformant via the classic narrow-pulse frame INT; hard regression guard
ULAvsSJS planned ULA timing comparison