zx_go emulator — conformance dashboard

Live conformance of the zx_go emulation core against its oracles and the external ZX Spectrum Next test suites. Generated from the manifest and the actual test run on every publish — do not edit by hand. Background: known-gaps register · Next FPGA emulation docs · VHDL conformance matrix.

Summary

pass 22 partial 2 skip 1

CPU (Z80)

CheckKindStatusOracle / tracking
zexdoc — documented Z80 instruction exerciser internal pass Cringle zexdoc
zexall — undocumented-flags Z80 instruction exerciser internal pass Cringle zexall
Z80N gate-level golden (GHDL simulation of the FPGA t80n core) internal pass t80n VHDL via GHDL
raxoft/z80test v1.2a — all six CPU variants
Stricter than zexall: all six variants pass 160/160 (Q register, block/OUTx flags and MEMPTR included) — see the breakdown page. z80ccfscr is manual-only.
external pass roadmap: ZX Play #r3 · breakdown

Audio

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AY / YM2149 FPGA golden internal pass audio/ym2149.vhd via GHDL
DAC / SounDrive FPGA golden internal pass DAC VHDL via GHDL

Memory / paging

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Memory paging FPGA golden internal pass zxnext.vhd memory mux via GHDL

Storage

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divMMC automap FPGA golden internal pass divmmc.vhd via GHDL
SD SPI master FPGA golden internal pass SPI VHDL via GHDL

Video (Next)

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Layer 2 address + pixel FPGA goldens internal pass layer2.vhd via GHDL
Tilemap render + below/text status FPGA goldens internal pass tilemap.vhd via GHDL
Sprite render FPGA golden internal pass sprites.vhd via GHDL
LoRes / Radastan FPGA golden internal pass lores.vhd via GHDL
Palette FPGA golden internal pass zxnext.vhd palette via GHDL
Video mixer (compositor) FPGA golden internal pass zxnext.vhd mixer via GHDL
Copper FPGA golden internal pass copper.vhd via GHDL

Interrupts / timing

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CTC channel FPGA golden internal pass ctc_chan.vhd via GHDL
IM2 daisy-chain FPGA golden internal pass peripherals.vhd / im2_*.vhd via GHDL

Peripherals

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Multiface FPGA golden internal pass multiface.vhd via GHDL
UART FPGA golden internal pass UART VHDL via GHDL
Keyboard / keymap FPGA golden internal pass keymap VHDL via GHDL

Boot

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NextZXOS cold boot end-to-end (skips when licensed ROMs are not staged) internal skip Real NextZXOS through the FPGA-bootrom chain

Meta

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VHDL conformance matrix (per-axis enumeration of the FPGA surface)
Hand-maintained matrix; open rows are listed in the document and mirrored in known-gaps.md.
manual partial · breakdown

Next acceptance

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MrKWatkins/ZXSpectrumNextTests — Z80N, sprites, Layer 2, mixing, Copper, DMA, ULA, interrupts, timing
Community acceptance suite with real-hardware reference screenshots. 35 tests in 8 groups — see the breakdown page. The .snx blocker is resolved (.snx = 48K SNA); classic tests plus the Z80N groups are live, the remaining Next-side tests are being wired group by group.
external partial roadmap: ZX Play #139 · breakdown
Threetwosevensixseven/ZXSpectrumNextTests — all five tests
All five tests pass (16 builds: upstream DMA binaries + sjasmplus ports of the Zeus-only sources). Found and pinned two emulator gaps en route: the palette power-on identity default and ULA-palette transparency.
external pass roadmap: ZX Play #140 · breakdown

Known gaps and simplifications

Rendered from docs/architecture/known-gaps.md — the hand-maintained register of deliberate differences from real hardware. Rows link work to the roadmap via the statuses and sources recorded there.

Video

GapStatusSource
Copper palette effects sample once per 7MHz pixel: the copper is cycle-paced (RunToCycle: MOVE=2 / NOOP=1 cycles at 28MHz) and interleaves per pixel with the live-palette ULA row render, but half-pixel colour detail (two MOVEs inside one pixel) collapses to one sample, top/bottom border rows resolve once per raster line (end-of-line palette state — colours are live, sub-line copper detail is not), and NON-ULA layers (L2/sprites/tilemap) still see copper state at whole-line granularityprecision limit (per-pixel sampling; surface pinned by TestNexttestsCopper)`pkg/next/copper/copper.go`, `pkg/ula/ula.go` (applyNextCompositor)
Sprite per-scanline bandwidth limit not modelled; $303B bit 1 (max per line) always reads 0deferred`pkg/next/sprite/doc.go`
Compositor blend modes 6/7 approximated as SLU in the scanline painter (the faithful mixer exists in `mixer.go` but the painter has not migrated onto it); tilemap `tm_below` per-pixel bit approximateddeferred`pkg/next/compositor/compositor.go`
Hi-res Layer 2 shows visible rows 0..239; the bottom 16 of the 256-line modes are cropped (off-window overscan)documented simplification`pkg/ula/ula.go` (renderHiResLayer2), ROADMAP
ULA inner screen + border now render through the LIVE Next ULA palette per pixel — colour redefinition AND transparency, ULANext + standard decode per zxula.vhd:483-558 (closed by the base/Copper work). Residue: Timex hi-res and the ULA-output-disabled fill keep the classic pre-render (live decode falls back to it), where transparency still relies on the legacy RGBA value-matching setclosed for the standard screen mode; Timex residue deferred to the Graphics/ULA groups`pkg/ula/ula.go` (renderNextULARow), `pkg/next/compositor/compositor.go` (ULARGBA)
Sprites composite 8 rows lower than the hardware paper position (the 256-line sprite frame is aligned to the 240-line canvas origin; the canvas draws 24 border lines where hardware shows 32)canvas simplification, constant offset`pkg/next/compositor/compositor.go`; observed via the ported Level2Order test
Turbo-speed video timing: pkg/ula scanline/border tracking ignores the speed multiplier, so border effects are wrong above 3.5 MHzdeferred`pkg/memory/memory.go` comment

NextReg / ports (see VHDL_CONFORMANCE.md for the full matrix)

GapStatus
NR$C0 programmable IM2 vector bits 7:5 unmodelled; IM status bits stored as 0deferred
NR$C4 reset default: expbus enable bit needs the composed read-back mux (flagged ❌ in the matrix)deferred
~30 composed read-backs ($68, $69, $C0, $C4, $C6, $CC-$CE, $A9, $0B...) not individually pinned to the VHDL muxaudit gap
Port $FF bit 6 (Timex/SCLD ULA-frame-INT disable) not implemented in WritePortconfirmed gap (matrix axis 4)
No exhaustive port-by-port VHDL decode conformance test; no single test enumerates all 256 write masksaudit gap
NR$02 iotrap read bit 4; NR$8C soft-reset latched low nibble; NR$0A DPI bits; NR$69 display-control bits stored but inertdeferred
Frame-origin offset (CPU tstate 0 vs ULA hc0/vc0) unvalidated; line-INT at turbo; IM2 vector table gates not all wiredaudit gap (matrix axis 5)

DMA, buses, peripherals

GapStatusSource
zxnDMA: interrupt/match logic and DMA-vs-CPU bus contention not modelled; descriptor mode (port $DB) deferred. Read/write cycle-length costs are charged in CPU T-states (the FPGA FSM ticks at 28MHz) — a documented model convention; the prescaler delay IS turbo-exact (prescaler*4^turbo/2 T-states, dma.vhd:250-255/424)deferred`pkg/next/dma/dma.go`
UART/ESP: AT responder only, no real networking or socket emulationout of scope`pkg/next/uart/doc.go`
NR$0B joystick I/O mode: register exact, pin-repurposing behaviour (GPIO/UART on joystick pins) not modelledout of scope`pkg/next/wire.go`
RTC: clock-register writes discarded (host time is truth); only NVRAM persists; 1 Hz output disabledpragmatic model`pkg/next/rtc/rtc.go`
divMMC $2009 FRAMES-bump stub and bank-1 stub write-protect emulate firmware-installed handlers non-literallypragmatic model`pkg/next/divmmc/divmmc.go`
esxDOS F_READDIR entry layout simplified; F_FSTAT fills size + dir bit only; no success-with-carry contractdeferred`pkg/next/esxdos/file_handlers.go`
.NEX loader: `Copper` field exists but is never populated (code states standard V1.2 carries no copper section, package doc says otherwise) — doc/implementation inconsistency to resolveneeds resolution`pkg/next/nex/nex.go` vs `doc.go`
ROM SHA-256 digests reported but not enforced as a boot gateplanned`pkg/next/install/install.go`
Audio event placement above 3.5 MHz is approximate (sample-exact placement is a known limit); Next DAC granularity notes in docs/spectrum-next.mddeferreddocs/spectrum-next.md

Classic line scope limits

ItemStatusSource
IF1 RS-232 and SinclairNET: stubbed as "no peripheral connected"; CTR WAT CPU-stall not modelledout of scope`pkg/if1/ula.go`
Floppy controllers are I/O-advanced: no rotational/seek timing (weak sectors and Speedlock are modelled on the +3)pragmatic modelfdc package docs
Beta density bit not modelled (TR-DOS always MFM)pragmatic model`pkg/betadisk/interface.go`
Pentagon-1024 mapping mode ($EFF7 reg 2) latched but not modelleddeferred`pkg/memory/memory.go`
TZX blocks 0x12/0x13/0x15 (pure tone / pulse sequence / direct recording) parsed but skippeddeferred`pkg/ula/tzx.go`
Floating bus returns $FF on +2A/+3/Next (correct) — noted here because it surprises peoplecorrect behaviour`pkg/ula/ula.go`
Multiface paging readback models $7F3F/$1F3F onlydeferred`pkg/ula/ula.go`
MEMPTR implemented to the depth zexall observes; some exotic update sites may be missing (only visible via F3/F5) — passes z80test v1.2a's memptr variant outrightdocumented depth`pkg/z80/z80.go`; `pkg/testharness/z80test_test.go`
Per-access memory contention (`MemContend`) off machine-wide; lump T-state totals are the shipping modeldeferred, gated on turbo contention work`pkg/z80/z80.go`
SAM: MIDI, clock port, SD/IDE ports ignoredout of scope`pkg/sam/io.go`
SAA1099 is datasheet-modelled (no hardware-verified reference core exists)best available`pkg/saa1099/saa1099.go`

Tooling and port gaps

ItemStatusSource
Time-travel ring captures CPU + visible 64K + ports + border only; upper RAM banks, divMMC RAM, NextRegs, MMU slots not captured/restored (phases 2a/2b catalogued)deferred`cmd/zx_go/timetravel.go`
wasm binary ~31 MB (Fyne linked as dead code); shrinking requires splitting the core out of `package main`later optimisation`wasm/STATUS.md`
Desktop run loop does not use the fastboot fast-forward (browser only)deferred`cmd/zx_go/fastboot.go`
The Next cannot tape-load in the browser player; .tap on the Next falls back to the 128Kdeferred`GoEmulator.js`
Browser direct-boot seed table and the nexload menu-index are coupled to the SD distro version; re-verification procedure documentedmaintenance coupling`packages/emulator-core/README.md`
Warm-boot path (`--warm-boot`) uses captured reference dumps; non-faithful by design, default offdev tool`cmd/zx_go/next.go`